Ali Khakifirooz
757Patents
25h-index
174Co-inventors
89Inventor score
Filing activity: Sep 24, 2009 → Mar 31, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8969934B1 | Gate-all-around nanowire MOSFET and method of formation | Electricity | 308 | Active |
| US7993999B2 | High-K/metal gate CMOS finFET with improved pFET threshold voltage | Electricity | 100 | Active |
| US9659963B2 | Contact formation to 3D monolithic stacked FinFETs | Electricity | 70 | Active |
| US8169025B2 | Strained CMOS device, circuit and method of fabrication | Electricity | 57 | Active |
| US8796093B1 | Doping of FinFET structures | Electricity | 52 | Active |
| US8524592B1 | Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices | Electricity | 44 | Active |
| US8703557B1 | Methods of removing dummy fin structures when forming finFET devices | Electricity | 42 | Active |
| US9293459B1 | Method and structure for improving finFET with epitaxy source/drain | Electricity | 39 | Active |
| US9312383B1 | Self-aligned contacts for vertical field effect transistors | Electricity | 38 | Active |
| US8951870B2 | Forming strained and relaxed silicon and silicon germanium fins on the same wafer | Electricity | 37 | Active |
| US9190471B2 | Semiconductor structure having a source and a drain with reverse facets | Electricity | 35 | Active |
| US9455331B1 | Method and structure of forming controllable unmerged epitaxial material | Electricity | 34 | Active |
| US8900951B1 | Gate-all-around nanowire MOSFET and method of formation | Electricity | 32 | Active |
| US8541274B1 | Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation | Electricity | 32 | Active |
| US9219154B1 | Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors | Electricity | 31 | Active |
| US9093533B2 | FinFET structures having silicon germanium and silicon channels | Electricity | 31 | Active |
| US9356027B1 | Dual work function integration for stacked FinFET | Electricity | 31 | Active |
| US8822320B2 | Dense finFET SRAM | Electricity | 30 | Active |
| US8486776B2 | Strained devices, methods of manufacture and design structures | Electricity | 29 | Active |
| US8841185B2 | High density bulk fin capacitor | Electricity | 29 | Active |
| US9196479B1 | Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures | Electricity | 28 | Active |
| US9257527B2 | Nanowire transistor structures with merged source/drain regions using auxiliary pillars | Electricity | 27 | Active |
| US8435845B2 | Junction field effect transistor with an epitaxially grown gate structure | Electricity | 26 | Active |
| US8207038B2 | Stressed Fin-FET devices with low contact resistance | Electricity | 26 | Active |
| US8921191B2 | Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same | Electricity | 25 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.