Gate contact structure for a trench power MOSFET with a split gate configuration
US12224342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2022 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Apr 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/2527
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.