Method of evaluating SiC substrate, method of manufacturing SiC epitaxial wafer, and method of manufacturing SiC device
US12228523B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 1, 2020 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jun 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This method of evaluating a SiC substrate includes a preparation step of preparing two or more SiC substrates obtained from the same SiC ingot grown from the same seed crystal, a defect position specifying step of specifying positions of defects in the substrates by observing a main surface of each of the two or more SiC substrates, and a comparison step of comparing the positions of the defects of the two or more SiC substrates, in which, in the preparation step, a SiC substrate positioned closest to the seed crystal is used as a reference wafer among the two or more SiC substrates, and the comparison step comprises a sub-step wherein a first defect of the reference wafer is compared with a second defect of a SiC substrate other than the reference wafer, it is judged whether a defect distance of the two compared defects in a [11-20] direction is 0.6 mm or more or less than 0.2 mm, and the two compared defects are determined to be defects not associated with the same threading defect when the defect distance is 0.6 mm or more, and the two compared defects are determined to be defects associated with the same threading defect when the defect distance is less than 0.2 mm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.