Semiconductor memory devices with diode-connected MOS
US12230338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2024 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Apr 4, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.