Carrier structure including pockets for accommodating semiconductor chip stack structure
US12230575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2021 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Dec 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A carrier structure including semiconductor chip stack structures; and a carrier tape including a plurality of pockets respectively accommodating the semiconductor chip stack structures, wherein each of the plurality of pockets includes a bottom surface, first sidewalls in four corner regions of each of the plurality of pockets, and second sidewalls between adjacent first sidewalls, each of the first sidewalls has a first portion having a first inclination angle and a second portion on the first portion and having a second inclination angle, the second inclination angle being greater than the first inclination angle, and vertices of lower surfaces of the semiconductor chip stack structures are in contact with the first sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.