Multi-device graded embedding package substrate and manufacturing method thereof
US12230581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jul 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4661
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.