Word line structure of three-dimensional memory device
US12232320B2 · kind B2 · utility
0Cited by
18References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2023 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Aug 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a substrate, a stack over the substrate, and a gate line slit extending along a first direction and dividing the stack into two portions. The stack includes a connection portion that connects the two portions of the stack. The connection portion includes at least two sub-connection portions along a second direction perpendicular to the first direction. The gate line slit includes at least two portions along the first direction. Each sub-connection portion is between adjacent two portions of the gate line slit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.