Patent · US Active

RRAM process integration scheme and cell structure with reduced masking operations

US12232335B2 · kind B2 · utility

0Cited by

8References

19Claims

0Family size

Assignee

Hefei Reliance Memory Limited · CN

Inventors

Zhichao Lu · San Jose, US
Brent Haukness · Monte Sereno, US

Key dates

Filing date	Aug 18, 2022
Grant date	Feb 18, 2025
Priority date	—
Expiry date	Feb 2, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG11C2213/77
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.