Memory system for controlling latency and method of operating the same
US12236092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Jan 24, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided herein may be a memory system and a method of operating the same. A memory controller may include a latency monitoring component configured to generate information about a number of occurrences of over-latency exceeding a preset reference latency among latencies each indicating a time amount required from a time point at which first command is received from an external device to a time point at which a completion response to the first command is transmitted to the external device during a first period, and a completion response controller configured to determine a first target latency based on the information about the number of occurrences of over-latency, and provide, during a second period following the first period, the external device with a completion response to a second commands provided from the external device after the first target latency has elapsed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.