Bank-level parallelism for processing in memory
US12236134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Sep 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.