Memory system including an interface circuit connecting a controller and memory
US12237046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Mar 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.