Semiconductor package and method of manufacturing semiconductor package
US12237240B2 · kind B2 · utility
0Cited by
5References
18Claims
0Family size
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Key dates
| Filing date | Jan 11, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Feb 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.