Substrates with solder barriers on leads
US12237249B2 · kind B2 · utility
0Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2018 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Oct 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system comprises a substrate. The substrate comprises a lead. The system also comprises a solder barrier formed on the lead. The solder barrier is to contain a solder bump within a solder area on the lead. The system further includes a solder bump in the solder area and a die having an active surface coupled to the solder bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.