CMOS logic element including oxide semiconductor
US12237331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2021 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Jul 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.