Topology synthesis of a network-on-chip (NoC)
US12237980B2 · kind B2 · utility
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49References
15Claims
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Key dates
| Filing date | Sep 10, 2021 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Aug 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.