In-memory zero value detection
US12242381B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2022 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Oct 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.