Memory array structure
US12243619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2022 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Jan 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.