Chip scale package (CSP) semiconductor device having thin substrate
US12243808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2022 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Feb 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 μm to 35 μm. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger than 150° C. The plurality of metal layers comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a metallic layer. In a first example, the metallic layer is a second titanium layer. In a second example, the metallic layer is a Titanium Nitride (TiN) layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.