Inventor · San Jose, CA, US

Jun Lu

104Patents
10h-index
80Co-inventors
79Inventor score

Filing activity: Nov 21, 2007 → Oct 5, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7884696B2 Lead frame-based discrete power inductor Electricity 37 Active
US8513784B2 Multi-layer lead frame package and method of fabrication Electricity 17 Active
US8581376B2 Stacked dual chip package and method of fabrication Electricity 16 Active
US8642385B2 Wafer level package structure and the fabrication method thereof Electricity 16 Active
US9653383B2 Semiconductor device with thick bottom metal and preparation method thereof Electricity 14 Active
US7898092B2 Stacked-die package for battery power management Electricity 13 Active
US9041172B1 Semiconductor device for restraining creep-age phenomenon and fabricating method thereof Electricity 12 Active
US8154108B2 Dual-leadframe multi-chip package and method of manufacture Electricity 11 Active
US8575006B2 Process to form semiconductor packages with external leads Electricity 11 Active
US8952509B1 Stacked multi-chip bottom source semiconductor device and preparation method thereof Electricity 11 Active
US7843303B2 Multilayer inductor Emerging Cross-Sectional Technologies 10 Active
US8481368B2 Semiconductor package of a flipped MOSFET and its manufacturing method Electricity 10 Active
US8344519B2 Stacked-die package for battery power management Electricity 9 Active
US7948346B2 Planar grooved power inductor structure and method Emerging Cross-Sectional Technologies 9 Active
US8436429B2 Stacked power semiconductor device using dual lead frame and manufacturing method Electricity 8 Active
US8778735B1 Packaging method of molded wafer level chip scale package (WLCSP) Electricity 8 Active
US9184117B2 Stacked dual-chip packaging structure and preparation method thereof Electricity 7 Active
US9437528B1 Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof Electricity 7 Active
US7884454B2 Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package Electricity 6 Active
US8564110B2 Power device with bottom source electrode Electricity 6 Active
US9054091B2 Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures Electricity 5 Active
US8076183B2 Method of attaching an interconnection plate to a semiconductor die within a leadframe package Electricity 5 Active
US8669650B2 Flip chip semiconductor device Electricity 4 Active
US7971340B2 Planar grooved power inductor structure and method Emerging Cross-Sectional Technologies 4 Active
US8247288B2 Method of integrating a MOSFET with a capacitor Electricity 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.