Devices, systems, and methods for stacked die packages
US12243850B2 · kind B2 · utility
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1References
20Claims
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Key dates
| Filing date | Aug 3, 2021 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Oct 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.