Optical receiving circuit
US12243862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2019 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Mar 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an optical receiver circuit which suppresses an unnecessary increase in impedance and occurrences of resonance and radiation noise and which produces preferable high-frequency transmission characteristics, a PD submount mounted with a PD chip and a chip capacitor and a TIA carrier mounted with a TIA chip are electrically connected to each other by a bonding wire. The chip includes an anode electrode pad and a cathode electrode pad, anode electrode-side ground pads are formed at positions that sandwich the pad, and cathode electrode-side ground pads are formed at positions that sandwich the pad. A wire electrically connects the pad and a signal pad for input of the chip to each other, a wire electrically connects the pad and the capacitor to each other, and a wire electrically connects the pads and the pads to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.