Address boundary functions for physical and localized addresses
US12248405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Oct 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.