Overlay layer for network of processor cores
US12248430B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2022 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | May 30, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems related to the efficient execution of complex computations by a multicore processor and the movement of data among the various processing cores in the multicore processor are disclosed. A multicore processor includes a set of processing cores and associated sets of processing pipelines, core controllers, routers, and network interface units. The multicore processor also includes a computation layer, for conducting computations using the set of processing cores, with executable instructions for the set of processing pipelines which are executed by the set of core controllers. The multicore processor also includes a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for the set of routers and the set of network interface units. The multicore processor also includes a set of programmable controllers, with executable instructions for reformatting computational data from the computation layer for transmission through the network-on-chip layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.