Small-area high-efficiency read-only memory (ROM) array and method for operating the same
US12250810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Jul 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.