Memory including error correction circuit and operating method thereof
US12253912B2 · kind B2 · utility
0Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2023 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Mar 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an operating method of a memory, and the operating method may include reading, from selected memory cells included in the memory, codewords including data and an error correction code; detecting errors in the codewords; correcting the errors in the codewords; re-writing the error-corrected codewords to the selected memory cells; re-reading the re-written error-corrected codewords from the selected memory cells; and determining whether the errors are permanent errors in response to a determination that an error is present in the re-read error-corrected codewords.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.