Patent · US Active

Result register with readout counter value

US12254212B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Tommaso Bacigalupo · San Jose, US
Marco Bachhuber · Dundenheim, DE
Michael Krug · Munich, DE

Key dates

Filing date	May 2, 2023
Grant date	Mar 18, 2025
Priority date	—
Expiry date	May 2, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06F3/0673
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit includes one or more datastores configured to store a result register and a readout counter value and logic circuitry coupled to the one or more datastores. The logic circuitry is configured to cause, for a cycle of a plurality of cycles of a periodic signal, one or more analog-to-digital converters (ADCs) to store data to the result register and modify the readout counter value in response to the one or more ADCs storing the data to the result register for the cycle. In response to a read request for the data at the result register for the cycle, the logic circuitry is configured to output the data stored by the result register, output the readout counter value for the cycle, and, after the output of the readout counter value, set the readout counter value to a predetermined value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.