Calibration method for emulating group III-V semiconductor device and method for manufacturing group III-V semiconductor device
US12254262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2021 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Dec 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/112
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.