Scalable toggle point control circuitry for a clustered decode pipeline
US12254319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Jul 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described. In one example, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, and a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster, wherein the toggle point control circuit is to: determine a location in an instruction stream as a candidate toggle point to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster, track a number of times a characteristic of multiple previous decodes of the instruction stream is present for the location, and cause insertion of a toggle point at the location, based on the number of times, to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.