Jonathan D. Combs
31Patents
4h-index
52Co-inventors
66Inventor score
Filing activity: Mar 13, 2001 → Dec 13, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7552254B1 | Associating address space identifiers with active contexts | Physics | 33 | Active |
| US9465680B1 | Method and apparatus for processor performance monitoring | Physics | 13 | Active |
| US8225046B2 | Method and apparatus for saving power by efficiently disabling ways for a set-associative cache | Emerging Cross-Sectional Technologies | 8 | Active |
| US9454371B2 | Micro-architecture for eliminating MOV operations | Physics | 6 | Active |
| US10067762B2 | Apparatuses, methods, and systems for memory disambiguation | Physics | 4 | Active |
| US6557898B2 | Device, system and method for labeling three-dimensional objects | Physics | 4 | Expired |
| US10331454B2 | System and method for load balancing in out-of-order clustered decoding | Physics | 4 | Active |
| US7783871B2 | Method to remove stale branch predictions for an instruction prior to execution within a microprocessor | Physics | 3 | Active |
| US9703566B2 | Sharing TLB mappings between contexts | Physics | 3 | Active |
| US10417001B2 | Physical register table for eliminating move instructions | Physics | 3 | Active |
| US9766999B2 | Monitoring performance of a processing device to manage non-precise events | Physics | 3 | Active |
| US9098284B2 | Method and apparatus for saving power by efficiently disabling ways for a set-associative cache | Emerging Cross-Sectional Technologies | 2 | Active |
| US9367317B2 | Loop streaming detector for standard and complex instruction types | Physics | 2 | Active |
| US12190157B2 | Methods, systems, and apparatuses for scalable port-binding for asymmetric execution ports and allocation widths of a processor | Physics | 1 | Active |
| US9804852B2 | Conditional execution support for ISA instructions using prefixes | Physics | 1 | Active |
| US9329865B2 | Context control and parameter passing within microcode based instruction routines | Physics | 1 | Active |
| US8656108B2 | Method and apparatus for saving power by efficiently disabling ways for a set-associative cache | Emerging Cross-Sectional Technologies | 1 | Active |
| US8904112B2 | Method and apparatus for saving power by efficiently disabling ways for a set-associative cache | Emerging Cross-Sectional Technologies | 0 | Active |
| US10592244B2 | Branch type logging in last branch registers | Physics | 0 | Active |
| US12254319B2 | Scalable toggle point control circuitry for a clustered decode pipeline | Physics | 0 | Active |
| US10579492B2 | Device, system and method for identifying a source of latency in pipeline circuitry | Physics | 0 | Active |
| US11907712B2 | Methods, systems, and apparatuses for out-of-order access to a shared microcode sequencer by a clustered decode pipeline | Physics | 0 | Active |
| US12423103B2 | Instruction decode cluster offlining | Emerging Cross-Sectional Technologies | 0 | Active |
| US12353881B2 | Circuitry and methods for power efficient generation of length markers for a variable length instruction set | Physics | 0 | Active |
| US8793469B2 | Programmable logic array and read-only memory area reduction using context-sensitive logic for data space manipulation | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.