Hierarchical hybrid network on chip architecture for compute-in-memory probabilistic machine learning accelerator
US12254399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2021 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Apr 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.