Memory cell with access device and memory capacitor structures
US12254914B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2023 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Dec 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/0036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.