Semiconductor structure and manufacturing method thereof
US12255095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2023 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | May 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76849
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.