Structure and method for isolation of bit-line drivers for a three-dimensional NAND

US12255164B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Liang Chen · 红钢城街道, CN
• Wei Liu · 红钢城街道, CN
• Cheng Gan · Hubei, CN

Key dates

• Filing date: Jun 27, 2022
• Grant date: Mar 18, 2025
• Expiry date: Jun 27, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the 3D memory device includes a peripheral circuitry formed on a first substrate. The peripheral circuitry includes a plurality of peripheral devices on a first side of the first substrate, a first interconnect layer, and a deep-trench-isolation on a second side of the first substrate, wherein the first and second sides are opposite sides of the first substrate and the deep-trench-isolation is configured to provide electrical isolation between at least two neighboring peripheral devices. The 3D memory device also includes a memory array formed on a second substrate. The memory array includes at least one memory cell and a second interconnect layer, wherein the second interconnect layer of the memory array is bonded with the first interconnect layer of the peripheral circuitry, and the peripheral devices are electrically connected with the memory cells.