Mirror image of geometrical patterns in stacked integrated circuit dies
US12255178B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Jan 26, 2022 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Aug 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.