Inventor · Pardes Hana-Karkur, IL

Ido Bourstein

29Patents
7h-index
19Co-inventors
62Inventor score

Filing activity: Jul 7, 2005 → May 1, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7330081B1 Digitally controlled oscillator and associated method Electricity 26 Expired
US7884646B1 No stress level shifter Electricity 22 Active
US8370654B1 AVS-adaptive voltage scaling Emerging Cross-Sectional Technologies 18 Active
US9006908B2 Integrated circuit interposer and method of manufacturing the same Electricity 13 Active
US7652516B2 Apparatus and method for generating a clock signal Physics 11 Active
US9337660B1 Switching arrangement for power supply from multiple power sources Electricity 9 Active
US10295740B2 Integrating silicon photonics and laser dies using flip-chip technology Electricity 8 Active
US8169234B1 No stress level shifter Electricity 7 Active
US7932768B2 Apparatus and method for generating a clock signal Physics 5 Active
US7592934B1 Method and apparatus for generating differential signal Electricity 4 Active
US8972755B1 AVS-adaptive voltage scaling Emerging Cross-Sectional Technologies 4 Active
US9455193B2 Integrated circuit interposer and method of manufacturing the same Electricity 2 Active
US7804431B1 Method and apparatus for generating differential signal Electricity 2 Active
US8615669B1 AVS—adaptive voltage scaling Emerging Cross-Sectional Technologies 2 Active
US9621303B2 Method and apparatus for valid encoding Electricity 1 Active
US9436203B2 Method and apparatus for regulator control Physics 1 Active
US9465396B2 AVS master slave Emerging Cross-Sectional Technologies 1 Active
US10436841B2 Use of wrapper cells to improve signal routing in integrated circuits Physics 1 Active
US7936182B1 Isolated level shifter Electricity 1 Active
US9086453B2 Method and apparatus for testing integrated circuits Physics 1 Active
US9606150B1 Sensing arrangement for sensing a voltage from multiple voltage sources Physics 0 Active
US11705427B2 Mirror-image chips on a common substrate Electricity 0 Active
US12255178B2 Mirror image of geometrical patterns in stacked integrated circuit dies Electricity 0 Active
US10915154B1 Raising maximal silicon die temperature using reliability model Physics 0 Active
US8866501B2 Method and apparatus for testing integrated circuits Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.