Field effect transistors with dual field plates
US12255235B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2021 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Apr 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor structure is provided, the transistor structure comprising a source, a drain, and a gate between the source and the drain. The gate may have a top surface. A first field plate may be between the source and the drain. The first field plate may be L-shaped and having a vertical portion over a horizontal portion. A top surface of the vertical portion of the first field plate may be at least as high as the top surface of the gate. A second field plate, whereby the second field plate may be connected to the gate and the second field plate may partially overlap the horizontal portion of the first field plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.