Inventor · South Burlington, VT, US

Johnatan A. Kantarovsky

32Patents
1h-index
33Co-inventors
49Inventor score

Filing activity: Nov 20, 2016 → Apr 11, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US11923446B2 High electron mobility transistor devices having a silicided polysilicon layer Electricity 1 Active
US11380759B2 Transistor with embedded isolation layer in bulk substrate Electricity 1 Active
US10217826B2 Apparatus of a metal-oxide-semiconductor (MOS) transistor including a multi-split gate Electricity 1 Active
US10923577B2 Cavity structures under shallow trench isolation regions Electricity 1 Active
US12046633B2 Airgap structures in auto-doped region under one or more transistors Electricity 0 Active
US12389622B2 High electron mobility transistor devices having a silicided polysilicon layer Electricity 0 Active
US12255235B2 Field effect transistors with dual field plates Electricity 0 Active
US11177158B2 Integrated circuit structure with semiconductor-based isolation structure and methods to form same Electricity 0 Active
US11616127B2 Symmetric arrangement of field plates in semiconductor devices Electricity 0 Active
US12183814B1 Multi-channel transistor Electricity 0 Active
US11380622B2 Method and related structure to authenticate integrated circuit with authentication film Electricity 0 Active
US12159910B2 Isolation regions for charge collection and removal Electricity 0 Active
US12416530B2 Temperature detection using negative temperature coefficient resistor in GaN setting Physics 0 Active
US12400927B2 High-mobility-electron transistors having heat dissipating structures Electricity 0 Active
US12119383B2 Transistor with multi-level self-aligned gate and source/drain terminals and methods Electricity 0 Active
US12243935B2 High electron mobility transistor devices having a silicided polysilicon layer Electricity 0 Active
US11881506B2 Gate structures with air gap isolation features Electricity 0 Active
US11574867B2 Non-planar silicided semiconductor electrical fuse Electricity 0 Active
US11316019B2 Symmetric arrangement of field plates in semiconductor devices Electricity 0 Active
US11646351B2 Transistor with multi-level self-aligned gate and source/drain terminals and methods Electricity 0 Active
US11054854B1 System and method to drive logic circuit with non-deterministic clock edge variation Electricity 0 Active
US11916119B2 Transistor with self-aligned gate and self-aligned source/drain terminal(s) and methods Electricity 0 Active
US11177345B1 Heterojunction bipolar transistor Electricity 0 Active
US12166476B2 High voltage device with linearizing field plate configuration Electricity 0 Active
US11710655B2 Integrated circuit structure with semiconductor-based isolation structure and methods to form same Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.