Patent · US Active

Concurrent support for multiple cache inclusivity schemes using low priority evict operations

US12259825B2 · kind B2 · utility

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20Claims

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Assignee

SiFive, Inc. · US

Inventors

Wesley Waylon Terpstra · San Mateo, US
Richard Van · Milpitas, US
Eric Andrew Gouldey · Fort Collins, US

Key dates

Filing date	Dec 20, 2023
Grant date	Mar 25, 2025
Priority date	—
Expiry date	Dec 20, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/084
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and methods are disclosed for concurrent support for multiple cache inclusivity schemes using low priority evict operations. For example, some methods may include, receiving a first eviction message having a lower priority than probe messages from a first inner cache; receiving a second eviction message having a higher priority than probe messages from a second inner cache; transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy; and, transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.