Systems and methods for address scrambling
US12259827B2 · kind B2 · utility
0Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2023 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | May 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system including memory, a lookup circuit and an address circuit. The memory can store a plurality of tables. Each table can have a plurality of entries and each entry can have an entry index. The lookup circuit can be coupled with the memory. The lookup circuit can provide the plurality of entry indexes of the plurality of tables to the address circuit. The address circuit can include a first circuit, a second circuit, and third circuit. The first circuit can include a plurality of entry scramblers. The second circuit can include a plurality of translators, and the third circuit can include a plurality of row scramblers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.