Memory system including multiple cores and method of operating the memory system
US12260119B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Dec 15, 2022 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Jan 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system according to the present technology includes a nonvolatile memory area, a buffer memory area temporarily storing data, and a plurality of cores configured to store, in the nonvolatile memory area, the data stored in the buffer memory area in response to a sudden power off, each of the plurality of cores outputting an interrupt signal indicating that the sudden power off is sensed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.