Systems and methods for performing multiplication of one or more matrices using multi-thread systolic arrays
US12260248B2 · kind B2 · utility
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Key dates
| Filing date | Feb 25, 2020 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Apr 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-thread systolic array includes a plurality of processing elements, each including a processor. Each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source; receive a plurality of second inputs from a respective second input source; the plurality of first inputs and the plurality of second inputs being arranged as a plurality of pairs corresponding to a plurality of threads; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads; and execute a computation operation for the certain thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.