Extended address interface activate sequence using mode register write
US12260931B2 · kind B2 · utility
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2References
18Claims
0Family size
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Key dates
| Filing date | Oct 13, 2022 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Jun 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a device is provided for implementing a mode register to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.