Component mounting system and component mounting method
US12261070B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 15, 2018 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Aug 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83874
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This chip mounting system simultaneously images an alignment mark disposed on a substrate (WT) and an alignment mark disposed on a chip (CP), with the alignment marks disposed on the substrate (WT) and the chip (CP) being separated by a first distance at which the alignment marks fall within a depth-of-field range of imaging devices. The chip mounting system calculates a relative positional deviation amount between the substrate (WT) and the chip (CP) from the imaged images of the alignment marks imaged by the imaging devices and, based on the calculated positional deviation amount, relatively moves the chip (CP) with respect to the substrate (WT) in a direction in which the positional deviation amount therebetween decreases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.