Method for mitigation of droop timing errors including a droop detector and dual mode logic
US12261600B2 · kind B2 · utility
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7Claims
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Key dates
| Filing date | Nov 18, 2021 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Nov 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to mitigate timing errors induced by power supply droops includes an inverter-based droop detector as well as Dual Mode Logic (DML) to achieve a droop-resist ant timing response. The droop detector is based on capacitor ratios and is thus less sensitive to Process/Voltage/Temperature (PVT) and to random offset than the prior art. The DML can alter its power/performance ratio based on the droop level input it receives from the detector, such that the critical timings are preserved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.