Ultra-low power adaptively reconfigurable system
US12261602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2022 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Apr 17, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.