Inter-PLL communication in a multi-PLL environment

US12261609B1 · kind B1 · utility

Assignee

• Shaoxing Yuanfang Semiconductor Co., Ltd. · CN

Inventors

• Srinath Sridharan · Nagamangala, IN
• Ankit Seedher · Kanchinakote, IN
• Raja Prabhu J · Kanchinakote, IN
• Purva Choudhary · Kanchinakote, IN
• Sandeep Sasi · Kanchinakote, IN
• Akash Gupta · Kanchinakote, IN
• Jeevabharathi G · Kanchinakote, IN
• Bhupendra Sharma · Kanchinakote, IN
• Debasish Behera · Kanchinakote, IN
• Nandini Ganig BS · Kanchinakote, IN
• Chandrashekar BG · Kanchinakote, IN

Key dates

• Filing date: Oct 18, 2023
• Grant date: Mar 25, 2025
• Expiry date: Oct 18, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/23
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An electronic block includes multiple independent Phase-Locked Loops (PLLs) and a switch matrix. Each PLL has an input path and an output path. The switch matrix is operable to concurrently connect a respective signal on the output path of each PLL to the input path of another PLL. In an embodiment, each of the respective signals on the output paths is a corresponding frequency-correction signal generated by a low-pass filter (LPF) in the corresponding PLL. In an embodiment, each PLL includes a frequency-correction signal combiner to combine the frequency-correction signals received from any of the other PLLs with its own frequency-correction signal to form a combined frequency-correction signal. The combined frequency-correction signal is provided to a controlled oscillator in the PLL to generate an output clock of the PLL based on the combined frequency-correction signal. The frequency-correction signals may be analog or digital signals.