Translating virtual memory addresses to physical memory addresses
US12265475B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 4, 2022 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Oct 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method includes accessing a virtual address from a request to access a memory of the computing device, where virtual addresses are translated to physical addresses of physical memory in the computing device using an N-level page table, and the lowest level of the page table contains page-table entries specifying the physical address of a frame of physical memory. The method includes searching, using the virtual address, a translation lookaside buffer (TLB) including a plurality of TLB entries, each TLB entry including (1) a tag identifying a virtual address associated with the entry and (2) a page-table entry specifying the physical address of a lower-level page table or of a frame of physical memory associated with the virtual address identified in the tag; and iteratively performing, until the virtual address is translated to a physical address, an address-translation procedure that depends on the cached TLB entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.