Refresh during power state changes
US12265732B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2023 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Oct 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0671
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor that is operable to be coupled to a memory includes a memory operation array, a controller, a refresh logic circuit, and a selector. The memory operation array is for storing memory operations for a first power state of the memory. The controller is responsive to a power state change request to execute a plurality of memory operations from the memory operation array when the first power state is selected. The refresh logic circuit generates refresh cycles periodically for the memory. The selector is for multiplexing the refresh cycles with the memory operations during a power state change to the first power state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.