NAND sensing circuit and technique for read-disturb mitigation
US12266406B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2021 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Aug 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5671
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through the string from the source line to the bitline. The voltage at a sensing node that is indicative of a threshold voltage of a memory cell can then be detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.