Memory device having row driver circuits for reducing leakage currents during power off
US12266418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2022 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Apr 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a memory device, including a plurality of memory banks. Each of the memory banks includes a memory array and a driver circuit. The driver circuit is coupled to the memory array, arranged to operably write data to the memory array according to write signals. The driver circuit includes a plurality of row driver circuits each coupled to a row of the memory cells. A global driver power circuit coupled to the row driver circuits in the plurality of memory banks to provide a global driver power. Each of the memory banks further includes a local driver power circuit coupled to respective row driver circuits in each of the memory banks to provide a local driver power. The local driver power circuit includes a first P-type MTCMOS coupled to a supply voltage and a control signal, controlled by the control signal to provide a local multi-threshold power signal to the respective row driver circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.